The present invention relates generally to a repair circuitry for a semiconductor device, and more particularly to a repair circuitry with an electrostatic discharge (ESD) protection device to prevent an electrical fuse from being mistakenly blown by an ESD event.
System-on-Chip (SoC) typically embeds memory IP cores with very large aggregate bit count per SoC. Because such memory IP cores are of high cell density, the embedded memories are more prone to defects that already exist in silicon substrate than any other component on the chip. New self-repair algorithm is therefore developed to test and repair embedded memory devices on SoCs. This new technology can improve typical SoC yields by as much as 82 percent over traditional external test and repair systems.
Such self-repair algorithms are usually achieved by applying electrical fuse circuits in semiconductor devices, such as chip ID, serial number, security key, analog trimming, memory redundancy, and boot ROM patch. The electrical fuses are programming silicided poly fuse, generally consist of, for example, polycrystalline silicon, or a similar suitable material that can be fused or melted through the action of energy. So, by passing a relatively large current through a particular electrical fuse, the electrical fuse will melt and disconnect a pre-programmed circuit. Eventually, the connection will go through another path, thereby reprogramming the circuit.
However, electrical fuses can be mistakenly programmed by stray currents during an ESD event. During an ESD event, charge is transferred between one or more pins of the integrated circuits and another conducting object in less than one microsecond. For instance, the market requirement for human-body mode ESD durability is 2 kilovolts. The standard human-body model assumes a static charge transfer of about 0.1 micro-Coulombs (10−7 C) upon static electricity discharge between a human and a chip. Such charge is relatively large as the gate oxide thickness is only about 10−6 cm. That means the electric fields in the gate oxide are on the order of 1013 v/cm. As a result, the electrical fuse can be easily brown by an ESD event in a very short time.
FIG. 1 shows a repair circuitry 100 for a memory IP core. The repair circuitry 100 includes an electrical fuse 102 coupled to a positive power supply (Vq) pad and a clamp circuit 101 consisting of two clamp diodes 107 and 108 for ESD protection. It is known that ESD stray current can flow over device surface or junctions. As illustrated in FIG. 1, ESD stray current can flow through path P1 or path P2. Even though the Vq pad has an ESD clamp circuit 101, some stray current may still flow through the fuse path P2. Referring to FIG. 1, PMOS transistor 103 is controlled by a bit-line (BL) and the NMOS transistor 104 by a word-line (WL). For path P2, if both the PMOS transistor 103 and the NMOS transistor 104 are at a turned-on or even weakly turned-on state during an ESD event, then the ESD stray current will flow through path P2 created by the electrical fuse 102, and accidentally blow the electrical fuse 102.
As such, what is needed is a new design of the repair circuitry that can automatically switch off its connection to the positive power supply pad when an ESD event occurs, and then automatically switch on its connection during normal operations.